1. Field of the Invention
The invention relates to a universal semiconductor wafer for high-voltage semiconductor components, in which at least one layer of a given conductivity type is provided on a semiconductor substrate of the given conductivity type. The invention further relates to a method of fabricating such a universal semiconductor wafer.
In order to be able to fabricate high-voltage semiconductor components, such as, for example, diodes, IGBTs (insulated gate bipolar transistors), MOSFETs or GTOs (gate turn-off thyristors), with the least possible outlay, a universal semiconductor wafer should be usable as a base material for all of these components. However, it has so far been necessary to optimize the respective base wafers for the individual, different high-voltage semiconductor components in accordance with the required voltage classes of the individual semiconductor components, for example by correspondingly doping the epitaxial layer and selecting a wafer thickness.
Current-switching semiconductor components for high voltages, such as IGBTs for example, are, especially if inductive loads are to be switched, more sensitive to interference, the higher the reverse or blocking voltage is. It is thus known that the operational reliability of high-voltage IGBTs, for example, is particularly jeopardized by cosmic radiation. In order to eliminate this susceptibility to interference, thought might be given to weakly doping the blocking region in the semiconductor wafer in order that high voltages can be blocked. However, limits are imposed on such a procedure because, if current flows at a high applied voltage, the charge carriers, which pass through the blocking region or the blocking path with a limiting velocity of.the order of magnitude of about 107 cm/s, are present in an extremely high concentration even with small current densities. This high concentration of charge carriers then comes close to the doping, so that a distortion of the electric field occurs, which can lead to destruction of the semiconductor component if the switched current assumes relatively high values. So far only thyristors have withstood high currents at a high reverse voltage. However, the thyristors have to be turned off in the event of a small applied voltage or a voltage inversion and can therefore not be regarded as xe2x80x9cgenuinexe2x80x9d switches.
2. Summary of the Invention
It is accordingly an object of the invention to provide a universal semiconductor wafer for high-voltage semiconductor components which overcomes the above-mentioned disadvantages of the heretofore-known wafers of this general type and which can be used in a diverse manner and is suitable especially for be high-voltage current switches which are to a large degree insensitive to cosmic radiation. It is a further object of the invention to provide a method of producing such a wafer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a universal semiconductor wafer for high-voltage semiconductor components, including:
a semiconductor substrate of a first conductivity type;
at least one layer of the first conductivity type disposed on the semiconductor substrate;
the at least one layer having a given layer thickness and forming an interface region between the at least one layer and the semiconductor substrate;
a plurality of floating semiconductor zones of a second conductivity type different from the first conductivity type, the floating semiconductor zones being embedded in the interface region; and
the floating semiconductor zones being spaced apart from one another by a given distance in the interface region, and at least one of the floating semiconductor zones having a given dimension substantially corresponding at most to the given distance and the given dimension being small compared to the given layer thickness of the at least one layer.
In other words, the object of the invention is achieved by virtue of the fact that a plurality of floating semiconductor zones of the second conductivity type are embedded in the interfaces between the semiconductor substrate and the layers. The zones are dimensioned in such a way that the dimension of a floating zone is small relative to the layer thickness of the layer and essentially corresponds to the distance between the conductive zones in an interface, or is smaller than the distance.
In this case, the individual layers may be epitaxial layers or be applied by direct wafer bonding. The floating semiconductor zones are preferably introduced by diffusion or ion implantation or implantation and subsequent diffusion into the surface of the configuration currently present, before the next layer is applied thereto by epitaxy or by direct wafer bonding.
Furthermore, the individual layers may preferably also be applied undoped and only subsequently be doped by neutron transmutation.
The semiconductor zones, which, if appropriate, may also be connected in a lattice-like manner, are preferably provided in a plurality of planes which are essentially parallel to one another. These planes are produced in a straightforward manner during the deposition of the individual epitaxial layers or during the application of the layers by direct wafer bonding. During the switching-on of a semiconductor component, for example an IGBT, using such a universal semiconductor wafer, in which a positive voltage is applied between gate and source, firstly a space charge zone or depletion zone is generated in the topmost semiconductor layer adjoining gate and source. If this space charge zone reaches the floating semiconductor zones bounding the topmost semiconductor layer with respect to the next semiconductor layer, then the voltage at these zones remains at the value Vpth which has been reached. This corresponds to a xe2x80x9cpunch-throughxe2x80x9d situation. If the voltage applied to the drain is increased further, the space charge zone or depletion zone forms in the second-uppermost semiconductor layer and finally reaches the second plane of the semiconductor zones. This operation is repeated until the space charge zone finally reaches a heavily doped zone of the first conductivity type on the side of the drain contact. As a result, a structure can thus be obtained which has N+1 times the dielectric strength of the same structure without semiconductor zones, if the number of planes of the semiconductor zones is given by N.
The one (first) conductivity type is preferably the n conductivity type, so that the other (second) conductivity type is given by the p conductivity type and the floating semiconductor zones are thus p-doped. It goes without saying, however, that doping with the conductivity types reversed is also possible.
In the last-mentioned example of an IGBT, the heavily doped semiconductor layer of one conductivity type, that is to say preferably an n+-conducting buffer layer, may also be replaced by another layer, for example by a so-called xe2x80x9cnon-punchthroughxe2x80x9d structure.
The semiconductor zones are doped in such a way that the space charge zones or depletion zones completely fill the individual semiconductor layers, when a voltage is applied, before a breakdown occurs. In this case, the doping of the semiconductor zones is high enough that they are not completely depleted. This applies preferably to the central region of the semiconductor component but not to the edge regions. There the doping of the semiconductor zones may be so low that they are depleted when the voltage is applied.
In accordance with another feature of the invention, additional floating semiconductor zones are disposed in a sporadic manner between the floating semiconductor zones. The additional semiconductor zones are of the first conductivity type and have a first doping concentration. The at least one layer of the first conductivity type has a second doping concentration smaller than the first doping concentration.
The universal semiconductor wafer according to the invention is suitable, in a particularly advantageous manner, for fabricating diodes, MOSFETs with a field plate edge or IGBTs and/or GTOs with planar edge structures, or else for other semiconductor components, such as, for example, xe2x80x9cNon-punch-through IGBTsxe2x80x9d with a rear side that has been ground to be thin.
With the objects of the invention in view there is also provided, a method for fabricating a universal semiconductor wafer, which includes the steps of:
providing a semiconductor substrate of a first conductivity type;
forming a plurality of floating semiconductor zones of a second conductivity type different from the first conductivity type in a boundary region of the semiconductor substrate by one of a diffusion step and an implantation step;
forming at least one layer of the first conductivity type on the semiconductor substrate; and
spacing the floating semiconductor zones from one another by a given distance such that a respective given dimension of the floating semiconductor zones substantially corresponds at most to the given distance and such that the respective given dimension is small compared to a given layer thickness of the at least one layer.
In accordance with another mode of the invention, the semiconductor zones are doped with a first doping concentration in a central region of the semiconductor substrate; and the semiconductor zones are doped with a second doping concentration smaller than the first doping concentration in an edge region of the semiconductor substrate.
In accordance with a further mode of the invention, further floating semiconductor zones of the second conductivity type are formed in boundary regions between the plurality of layers.
In accordance with another mode of the invention, lifetime killers, such as platinum or gold, are implanted, introduced or provided in any other way at interface regions between the it plurality of layers.
In accordance another mode of the invention, the universal semiconductor wafer according to the invention is used in a diode, a MOSFET, an IGBT, a GTO or any other switching device.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a universal semiconductor wafer for high-voltage semiconductor components and in a method of fabricating such a wafer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.